p2 Innovation in Solid State Devices for Exascale Computing

ABSTRACT
The continuous scaling of CMOS technology has enabled system performance to double every two years for the past 40 years

Introduction

Silicon CMOS Scaling

(page 1 col 2)
Gate length scaling began anew with the introduction of highk/
metal gate technology starting at 45nm.

For technology nodes beyond 11 nm requiring gate lengths
shorter than 10 nm, fully-depleted devices with ultra-thin bodies will
be needed to maintain acceptable short-channel effects (SCEs).

Lithography Scaling
(page 2)

The industry has addressed the lack of wavelength scaling
through an increase in the process complexity of the lithographic
process.

Extending beyond Silicon
Sooner or later, scaling limitations will destine CMOS to a
conclusion
(page 2 col 2)

Phase Change Memory
Exascale computing demands the movement of data among
possibly hundreds of millions of processor cores executing
massively parallel algorithms.

The access device of a PCM cell can be a planar NMOSFET
[24], PNP bipolar transistor, PN diode, vertical NMOSFET or
stackable 3D diode as shown in Figure 7.

Silicon Photonics
(p3)
Figure 10 illustrates a concept [27] of a 3D integrated [32]
microprocessor chip with a lower layer having hundreds of
processing cores, an intermediate memory layer (or multiple
memory layers) and an optical interconnect layer on top of the 3D
stack. The optical layer consists of 1000s of front-end CMOS
nanophotonic detectors, modulators, wavelength filters and optical
switches as well as corresponding analogue and digital CMOS
circuits.

3-D Silicon Stacking with TSV